Switched capacitor differential circuits are generally used to provide differential inputs to operational amplifiers, and can be connected in the form of a feedback circuit and are generally switched by two out-of-phase clock signals to switch the two separate input signals to the operational amplifier.
As best shown in FIG. 1, a known system includes a switched capacitor circuit 20 for switching differential input signals V.sub.inp1 and V.sub.inp2 into first and second inputs A and B of an operational amplifier 32. Switched capacitor circuit 20 receives two control inputs consisting of a first phase control clock signal PHI0 and a second phase control clock signal PHI1 that is non-overlapping with the first phase control clock signal PHI0.
The switched capacitor circuit 20 has a first input coupled to receive input signal V.sub.inp1 and a second input coupled to receive input signal V.sub.inp2 and a third input coupled to receive an analog ground signal AG. Analog ground AG is a voltage reference relative to which the input signals V.sub.inp1 and V.sub.inp2 change. The switched capacitor circuit 20 has a first output coupled to the first input A of the amplifier 32 and a second output coupled to the second input B of the amplifier 32.
Switched capacitor circuit 20 includes a first pair of switching transistors 22 and 23 which both have their gate electrodes connected to the first phase control clock signal PHI0, their respective source electrodes connected to the first and second inputs, respectively, and their respective drain electrodes connected to respective first electrodes of first and second respective capacitors 30 and 31.
A second pair of switching transistors 24 and 25 both have their gate electrodes connected to the second phase control clock signal PHI1, their respective source electrodes connected to the first and second outputs, respectively, and their respective drain electrodes connected to respective second electrodes of the first and second respective capacitors 30 and 31.
A third pair of switching transistors 28 and 29 have their gate electrodes coupled to the second phase control clock signal PHI1, their source electrodes coupled to the third input AG and their respective drain electrodes coupled to the respective first electrodes of the respective capacitors 30 and 31.
A fourth pair of switching transistors 26 and 27 have their gate electrodes coupled to the first phase control clock signal PHI0, their source electrodes coupled to the third input AG and their respective drain electrodes coupled to the respective second electrodes of the respective capacitors 30 and 31.
In operation, the switched capacitor circuit 20 charges capacitor 30 from the first input V.sub.inp1, and capacitor 31 from the second input V.sub.inp2, during an active period of the first phase control clock signal PHI0. During the active period of the second phase control clock signal PHI1, capacitor 30 is discharged to the analog ground AG and its charge transferred to the first output, and the charge on capacitor 31 is similarly transferred to the second output. However, since the voltage on the gate electrodes of transistors 22 and 23 is constant while that on their drain and source electrodes is changing according to the input signals, the source-drain ON resistance is also changing according to the input signal. Therefore, the RC constant for charging the capacitors also changes according to the input signal. Thus, the two differential paths are not equal if the input signals are not equal.
Attempts to solve this problem have been disclosed in, for example United Kingdom Patent Specifications GB 2 264 011 and GB 2 249 233, but neither has been very successful in solving the problem with a minimum of extra components.